Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including a buried-type gate.
A semiconductor memory device comprises a plurality of unit cells, each including one capacitor and one transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor according to a control signal (word is line) using the characteristics of a semiconductor to change the electrical conductivity according to an environment. The transistor is composed of three regions including a gate, a source, and a drain. Charge transfer occurs between the source and the drain according to a control signal input to the gate. The charge transfer between the source and the drain is achieved through a channel region using the characteristics of the semiconductor.
In a semiconductor device a transistor is disposed on a semiconductor substrate. After a gate is formed on the semiconductor substrate, impurities are doped on both sides of the gate to form a source and a drain. In this case, a space between the source and the drain under the gate becomes a channel region of the transistor. The transistor having a horizontal channel region occupies a given area of the semiconductor substrate. In the case of a complicated semiconductor memory device, it is difficult to reduce the whole area due to a plurality of transistors included in the semiconductor memory device.
When the whole area of the semiconductor memory device is reduced, the number of semiconductor memory devices which can be produced per wafer may be increased to improve the productivity. In order to reduce the whole area of the semiconductor memory device, various methods have been suggested. Of these methods, a recess gate is used instead of a conventional planar gate having a horizontal channel region. A recess is formed in a substrate, and a gate is formed in the recess, thereby obtaining the recess gate including a channel region along the curved surface of the recess. Moreover, a buried gate obtained by burying the whole gate in the recess has been researched.
In the buried gate, the whole gate is buried below the surface of the semiconductor substrate, thereby securing the length and the width of the channel. Also, in comparison with the recess gate, the buried gate can reduce the parasitic capacitance generated between the gate (word line) and the bit line by 50%.
However, when the buried gate process is performed on the entire structure of a cell region and a peripheral region, a space (height) of the cell region remains relative to the height where the gate of the peripheral region is formed. As a result, it matters how this height difference is used. In the prior art, (i) a cell region space corresponding to the gate height is empty, or (ii) a bit line of the cell region is formed together when the gate of the peripheral region is formed (gate bit line; GBL).
However, (i) when the space of the cell region is empty, the height of the storage node contact plug becomes higher in the cell region. As a result, a storage node contact hole is required to be formed deep, thereby increasing the difficulty of forming a bit line. (ii) When the bit line of the cell region is formed along with the gate of the peripheral region (GBL), an electrode of the bit line of the cell region is formed of the same material which forms a gate electrode in the peripheral region. Thus, the bit line in the cell region contains a barrier metal layer as well. As a result, the height of the bit line becomes higher, thereby increasing the parasite capacitance of the cell region.